The present invention generally relates to a circuit layout of a semiconductor memory, and more specifically, to a circuit layout of a semiconductor memory and a method for reducing defects of chemical mechanical polishing process.
Chemical mechanical polishing (CMP, or chemical mechanical planarization) is a planarization method of a semiconductor wafer""s surface as well as one of the most valuable technology of manufacturing integrated circuits in recent years. It is also the critical technology of precision manufacture in the future. The CMP technology was successfully developed, as developing CMOS by IBM company in 1985. The CMP technology is utilized to planarize dielectric layers or metal layers, concave or convex upon the wafer""s surface.
As the integrated circuit device is becoming smaller, with multi-layer conductive lines and with high density, the process limitation of the depth of focus (DOF) in the photolithography process is also becoming higher. Especially as semiconductor products, such as RAM or logical circuits, have three, four or more metal layers, the planaration technology is becoming more important than before. The CMP technology is so called because of mechanical pressure of the polishing head exerted on the wafer""s surface, as well as the chemical reaction of polishing slurry reacting on the wafer""s surface.
In the CMP equipment, the polishing head is used to press the wafer on the polishing pad and to drive the wafer rotating, while the polishing pad rotates in the opposite direction. During polishing, the polishing slurry, comprising polishing particles, will be delivered between the wafer and the polishing pad. The parameters having influences upon the CMP process comprising: the polishing pressure exerted by polishing heads and topography of wafers, rotation speeds of wafers and polishing heads, compositions of polishing particles and polishing slurry and the material of the polishing pad and its abrasion hardness, and so forth.
Referring to FIG. 1, a top view diagram is illustrated to show dielectric and conductive layers convex upon a semiconductor wafer. More specifically, in one of circuit structure layers on the wafer""s substrate 10, there are a plurality of parallel strips of circuit structure 20 convex upon the semiconductor wafer. The convex circuit structure 20 can be, for example, control gates, i.e., word lines, which can rewrite data into flash memory cells by controlling the control gate""s voltage. Diffusion areas 30 are located on substrate 10 between two strips of circuit structure 20 and are utilized to form source regions and drain regions. In addition, an isolating structure 40 is fabricated in the substrate 10 to isolate active regions for each memory cell. The isolating structure 40 can be a field oxide layer formed by LOCOS method, and preferably be a shallow trench isolation (STI) structure.
Continue to refer FIG. 1, four parallel strips of circuit structure 20 is shown. In the process of CMP, the pressure exerted on the front ends and the rear ends of the four strips of circuit structure 20 by the polishing head is not identical with on the other parts. Compared with the other parts, the force directions, on the front ends and the rear ends, are not uniform and come from many directions. Furthermore, the stresses of both ends are also larger than of the other parts. Accordingly, in the CMP process, corners of the front ends and the rear ends of the strips of circuit structure 20 are easily destroyed.
The method to improve the CMP process defects has two ways. One is to improve the control method of the CMP process conditions, such as the uniform polishing pressure, compositions of polishing particles or materials of the polishing pad. The other is to improve the structure strength of wafer""s circuits for reduce the possibility of generating defects in the CMP process to promote the yield and throughput.
According to the above mentioned, defects are easily formed in the CMP process on semiconductor wafer""s structure and result in semiconductor device""s performance degradation. Therefore, it is an objective of this invention to provide a process and a circuit layout of a semiconductor memory suitable for a chemical mechanical polishing process.
It is another objective of this invention to provide a circuit layout of a semiconductor memory suitable for a chemical mechanical polishing process to reduce defects in the CMP process. The circuit layout on a semiconductor wafer""s substrate comprises a plurality of strips of first circuit structure located and at least two strips of second circuit structure, respectively linking the front end and the rear end of first circuit structure, utilizing to average polishing pressure performing upon the front end and the rear end of first circuit structure during the chemical mechanical polishing process for reducing defects occurred.
The present invention also provide a method of forming a circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical polishing process. The method comprises to form a plurality of strips of first circuit structure located on the substrate of the semiconductor wafer. Then, form at least two strips of second circuit structure located on the substrate of the semiconductor wafer, wherein each of the two strips of second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure, utilizing to average polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during a chemical mechanical polishing process for reducing defects occurred.